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IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Truth Table III — Interrupt Flag (1)
Left Port
Right Port
Industrial Temperature Range
A 12L -A 0L
L
R/ W L
L
X
X
X
CE L
L
X
X
L
OE L
X
X
X
L
1FFF
X
X
1FFE
(4)
INT L
X
X
L (3)
H (2)
R/ W R
X
X
L
X
CE R
X
L
L
X
OE R
X
L
X
X
A 12R -A 0R (4)
X
1FFF
1FFE
X
INT R
(2)
H (3)
X
X
Function
Set Right INT R Flag
Reset Right INT R Flag
Set Left INT L Flag
Reset Left INT L Flag
NOTES:
1. Assumes BUSY L = BUSY R = V IH .
2. If BUSY L = V IL , then no change.
3. If BUSY R = V IL , then no change.
4. A 12X is a NC for IDT70P248, therefore Interrrupt Addresses are FFF and FFE.
Truth Table IV — Address BUSY
Arbitration
5675 tbl 15
Inputs
Outputs
CE L
X
H
X
L
CE R
X
X
H
L
A 0L -A 12L
A 0R -A 12R
NO MATCH
MATCH
MATCH
MATCH
BUSY L (1)
H
H
H
(2)
BUSY R (1)
H
H
H
(2)
Function
Normal
Normal
Normal
Write Inhibit (3)
NOTES:
5675 tbl 16
1. Pins BUSY L and BUSY R are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT70P258/248 are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. V IH if the inputs to the opposite port became stable after the address
and enable inputs of this port. If t APS is not met, either BUSY L or BUSY R = LOW will result. BUSY L and BUSY R outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSY L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSY R outputs are driving LOW regardless of actual logic level on the pin.
17
6.42
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